1. Field of the Invention
The present invention relates to the field of circuit design and, more particularly, to a decode register with scan functionality.
2. Description of the Related Art
One common operation performed by digital circuits is decoding. For example, combinations of high and low logic states on three input address lines conveyed to a memory unit may control up to eight output word lines via a decoder circuit. To add greater functionality, the decoder circuit may select from two or more inputs through the use of a multiplexer, as shown in FIG. 1A, which depicts a decoder circuit 100.
As illustrated, decoder circuit 100 includes registers 110A, which each receive one of three data in lines 102A and clock signal 112. Decoder circuit 100 further includes registers 110B, which each receive one of three data in lines 102B as well as clock signal 112. The outputs of registers 110A-B are conveyed to a multiplexer 120, which also receives select signal 104. The output of multiplexer 120 is conveyed to decode logic block 130, which performs a 3:8 decode function. One of the eight signals of decoded output bus 132 is thereby asserted as the output of decoder circuit 100 in response to the logic states of the three input signals.
One disadvantage of decoder circuit 100 is the large "clock-to-Q" delay. That is, while the setup time for decoder circuit 100 is minimal, the inputs signals 102 must propagate through three stages of logic to reach the output, decoded output bus 132, thereby increasing delay.
Turning now to FIG. 1B, a decoder circuit 140 is depicted. Decoder circuit 140 includes several logic blocks similar in function to those pictured in FIG. 1A, and are thus numbered identically. As shown, decoder circuit includes multiplexer 120, which selects between data in signals 102A-B based on the value of select signal 104. The output of multiplexer 120 is conveyed to decode logic 130, which performs a 3:8 decode function. The output of decode logic 130 is coupled to registers 110C, which convey output upon decoded output bus 132.
While decoder circuit 140 has reduced clock-to-Q delay with respect to circuit 100, the setup time has increased, thus maintaining a similar propagation delay. Another disadvantage of decoder circuit 140 is incorporating scan functionality. Scan functionality is included in logic circuits such as decoder circuit 140 in order to increase testability. In a scan mode, a number of devices (such as each of registers 110C) are coupled by connecting a scan output of one device to a scan input signal of another, forming a serial "scan chain". A bit stream is then clocked into a given scan chain while in scan mode, setting the corresponding logic devices into a desired state. A system clock is applied, causing the logic circuits to evaluate the data at their inputs. The resulting bit stream is then scanned out to check for proper operation.
Testing decoded output bus 132 within decoder circuit 140 in scan mode requires a number of scan bits equal to the number of register values driven on the bus (in this particular embodiment, eight). In order to test a particular decoded output bus signal 132, a particular bit sequence is first scanned in which specifies one of the eight output lines. Next, a system clock is applied, causing the chosen output line to be activated. Another scan chain may be evaluated to check the results.
Certain circuits require that scan in values be controlled such that only one signal on the output bus is active at any time. One example is a memory decoder which receives addresses and selects one of a plurality of word lines as a result. For proper operation of a memory array, only one word line at a given time may be activated. If more than one word line is active, incorrect data may be returned (or damage to the memory array may result).
The configuration of decoder circuit 140 does not insure that only one signal of decoded output bus 132 is active at a given time, however. Consider the case in which the eight-bit scan string of decoder circuit 140 is part of a larger scan chain. It may be necessary to scan particular values (e.g., two consecutive 1's) through circuit 140 to subsequent scan chain locations such that these values would cause two or more signals on decoded output bus 132 to be active during a given cycle. The reliability and testability of circuit 140 are thus compromised.
A faster decode register which performs a scan function that does not allow more than one output active at a time is therefore desirable.